The TCLS architecture allows for transparent, quicker and more reliable resynchronization of the CPUs in the event of an error as the erroneous CPU can be identified by comparing its outputs, and the correct architectural state can be restored from one of the other two functionally correct CPUs.
The TCLS architecture adds a third redundant CPU unit to the DCLS Cortex-R5 system to achieve fail functional capabilities and hence increase the availability of the system. This paper introduces the ARM Triple Core Lock-Step (TCLS) architecture, which builds up on the industry success of the ARM Cortex-R5 Dual-Core Lock-Step (DCLS) processor currently used in safety-critical real-time applications. Moreover, it can also apply to general heterogeneous quad-core System on Chip (SoC) with FPGA processor’s anti-SEU design and provides some ideas for further study of system level radiation-resistant chips’ design. It costs 27%-44% more time to process error and the system has relatively low resource utilization rate and power consumption. This combination brings us a promising result of fault identification and correction according to the simulation of the single channel data fault and the double channel data fault. Based on Xilinx Zynq Ultrascale+ MPSoC, we combine TMR with rolling back, watchdog and scrubbing technique between heterogeneous cores which are Arm Cortex-A53 and Field Programmable Gate Array (FPGA). To solve the problem of commercial device with weak anti-SEU ability and traditional radiation hardened device with slow processing speed, this article proposes a novel system-level collaborative triple module redundancy (TMR) design to mitigate single event upset (SEU) on the advanced heterogeneous processor.
0 kommentar(er)
